1. Field of the Invention
This invention relates to a signal processor for digitizing and processing video signals.
2. Description of the Prior Art
For a video display of moving objects without perceptible jerky movement, it is required that a predetermined number of frames per unit time be displayed, for example, 60 frames per second.
A prior art system shown in FIG. 1 has been employed for digitizing and processing video signals. Line 1, carrying a conventional composite video signal VI including horizontal and vertical synchronization signals and an encoded color or chrominance signal, is connected to an input of a decoder 2 which detects and separates the horizontal and vertical synchronizing signals H, V and which, from the intensity and chrominance signals, generates separate red, green and blue color intensity signals R, G, B. The color intensity signal outputs R, G, B of the decoder 2 are connected to respective inputs of an analog-to-digital (A/D) converter circuit 3 having A/D converters for each signal R, G, B to convert the color signals R, G, B into parallel digital signals R', G', B'. The digital outputs R', G', B' of the converter circuit 3 are connected to a large word (24-bit) port or parallel input of a frame memory which is operated by a timing and addressing circuit 10 to store the successive digitized color signals R', B', G' for one or more frames. A DMA controller and bus interface circuit 5 is connected to a small word (8-bit) port of the frame memory 4 for transferring data D from the frame memory 4 to a main memory 7 or a disc controller 8, and vice-versa, over a data bus 11 which is also connected to a computer 6. A program control channel (PCCH) 12 is connected to the interface 5, computer 6, main memory 7 and disc controller 8 for carrying various address, control and timing signals used to control the transfer of data D from one of the units 5, 6, 7 and 8 to another of these units, and to enable and disable the timing and addressing circuit 10 under the control of the computer 6. The memory 7 contains programs and data for the computer 6. A disc 9 is operated by the disc controller 8 for storing data. The timing and addressing circuit 10, controlled by signals on PCCH 12 and bus 11 as well as by the sync signals H, V, generates the timing and control signals needed to operate the analog-to-digital converter circuitry 3 to generate the successive large word digits of the parallel signals R', G', and B' and to operate the large port input of frame memory 4 to store these signals for each desired frame. A large port output of the frame memory 4 also operated by the timing and addressing circuit 10 is connected to inputs of a digital-to-analog (D/A) converter circuit 13 which contains D/A converters operated by timing signals from unit 10 for each of the processed intensity digital signals R", G", B" to generate analog output signals which can be applied to an encoder 14. The timing circuit 10 also generates output horizontal and vertical synchronizing signals H', V' which are applied to encoder 14 to regenerate a composite video signal VO on an output line 1' for being applied to a color monitor (not shown) to display a processed frame or frames stored in memory 4.
In operation of the video signal processor of FIG. 1, the video signal VI is decoded by the decoder 2 and separated into separate red, blue and green color intensity signals R, B, G. After the timing circuit is enabled by the computer 6 and initialized by a vertical sync pulse, these color signals are converted into respective parallel series of digital color signals R', B', G' by the A/D converter circuitry 3 over a time segment corresponding to one picture frame. The successive large word bytes forming the respective digital color signals R', B', G' are written in the frame memory 4 at successive addresses determined by address counting in circuit 10 for a complete frame. When a complete frame has been stored in the memory 4, the bytes of this frame are transmitted to the main memory 7 by DMA (direct memory access) and interface circuit 7 under control of the computer 6. The data transmitted to the memory 7 is then subjected to picture processing by the computer 6 which reads and writes the data bytes over bus 11 in accordance with address and control signals on PCCH 12. The processed bytes forming a picture frame are sent to the disc controller 8 by DMA over bus 11 and stored on the disc 9. Data stored in the disc 9, or in the memory 7, is transmitted to the frame memory 4 by way of the bus 11 and the DMA control and interface 5. Processed data forming digitized color signals R", G", B" are transferred in parallel streams under the control of unit 10 to the D/A converter circuitry 13 which produces the output analog red, green and blue signals for being combined with the horizontal and vertical synchronizing signals by encoder 14 to produce the composite color video signal VO which may then be displayed on a color monitor (not shown).
In the conventional system as described above and employing an NTSC input signal VI, a display picture frame has a matrix of pixels formed by 480 rows and 512 columns with each pixel formed by 3 bytes, one 8-bit byte for each of the red, green and blue intensity components. The bus 11 is constituted by an 8-bit data bus and the transmission speed of DMA bus interface is 64k bytes per second which thus results in the following time T required for transferring one picture frame to the main memory 7: ##EQU1## Further, a similar period of time is required to transfer data forming a processed picture frame back to the frame memory 4 through DMA interface 5. Accordingly, the input of a picture frame from the video signal VI, and the outputting of the processed data back to the frame memory for use in generating the display video signal VO requires a duration of more than 22 seconds. The conventional DMA interface 5 under control of the computer 6 can only transmit data at a rate of about 64k bytes per second. Further, during the transmission of data through DMA interface 5 to and from the main memory 7 or the disc controller 8, the DMA unit 5 seizes control of the bus 11 and the computer 6 cannot perform any processing which requires the use of bus 11.